The present invention relates to the simulation of electrical circuits, more particularly the simulation of interconnect lines on integrated circuits.
Integrated circuits such as very large-scale integrated (VLSI) circuits consist of a large number of transistors connected by several layers of metal formed into connecting lines. For example, programmable logic devices include hundreds of thousands or millions of devices connected together by 8 or more levels of interconnect. These programmable logic devices are programmed to provide a specific function by varying the interconnect paths using pass gates and other programmable interconnecting circuits. The result is that a single programmable logic device includes a variety of interconnecting paths.
These paths contribute parasitic or stray capacitances and resistances at the output of drivers on the integrated circuit. For example, each trace forms a capacitor to other traces, particularly those above, below, and to the side of it, to nearby devices, and to the substrate. Each trace also has a series resistance associated with it. Interconnect traces of different widths and lengths have different stray capacitances and resistance associated with them.
Before an integrated circuit is sold to a customer or programmed for use in a system, it is simulated to ensure proper functionality in the end product, particularly given various temperature and supply variations that the device may experience. For many years, circuit designers simply modeled interconnect traces as capacitors, when they were modeled at all. But as integrated circuit technology has progressed, and devices have gotten smaller while the number of metal layers has increased, other parasitics associated with interconnect lines, such as series resistance, and to a lesser extent inductance, have become more important and can no longer be ignored if accurate simulation results are needed.
But including the parasitic resistances and capacitances in a simulation is very complex and time consuming. First, these parasitics need to be accounted for, that is they need to be modeled. Second, they need to be included in the simulation itself, and doing so greatly increases the complexity of the circuit, the number of nodes, and run time of the simulation. Thus, what is needed are methods and apparatus for modeling and including these parasitics in circuit simulations without greatly slowing the simulation process.